ST & T UPSD3212C manuali

St t UPSD3212C Manuale Utente (163 pagine)

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FEATURES SUMMARY

1

Table 1. Device Summary

2

TABLE OF CONTENTS

3

SUMMARY DESCRIPTION

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Figure 3. TQFP52 Connections

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Figure 4. TQFP80 Connections

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52-PIN PACKAGE I/O PORT

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ARCHITECTURE OVERVIEW

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Program Memory

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ACC DPTR

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3Ah 1E73h

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Table 5. Logical Instructions

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byte. The jump dis

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AI07426b

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MCU MODULE DISCRIPTION

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Table 16. List of all SFR

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Register Name

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INTERRUPT SYSTEM

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Figure 16. Interrupt System

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POWER-SAVING MODE

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I/O PORTS (MCU MODULE)

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PORT Type and Description

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pull-ups

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OSCILLATOR

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SUPERVISORY

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WATCHDOG TIMER

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Reset period

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(1.258 second at 40Mhz)

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(about 6.291 seconds at 8Mhz)

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76543210

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Note: ↓ = falling edge

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SM0 SM1 SM2 REN TB8 RB8 TI RI

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Table 46. ADC SFR Memory Map

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Table 48. ADC Clock Input

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PULSE WIDTH MODULATION (PWM)

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C INTERFACE

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USB HARDWARE

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PSD MODULE

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DEVELOPMENT SYSTEM

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PSD MODULE DETAILED OPERATION

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MEMORY BLOCKS

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■ Program a Byte

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■ RESET to READ Mode

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Table 82. Instructions

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AI01369B

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AI01370B

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AI02867D

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Figure 54. PLD Diagram

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2. Inputs from the MCU module

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I/O PORTS

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CPLD MACROCELLS

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INPUT MACROCELLS

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AND ARRAY

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PLD INPUT BUS

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I/O PORTS (PSD MODULE)

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from the

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Note: 1. NA = Not Applicable

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POWER MANAGEMENT

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OPTIONAL

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INITIAL DELIVERY STATE

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■ PLD Timing

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■ MCU Module Timing

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= 5.0V (Turbo Mode Off)

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MAXIMUM RATING

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EMC CHARACTERISTICS

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(International standards)

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DC AND AC PARAMETERS

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Table 113. Major Parameters

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A0-A7 from

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RI or DPL

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Error ±2 l.s.b

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INPUT TO

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ENABLE/DISABLE

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2. CLKIN (PD1) t

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ISC OUTPUTS/TDO

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AI03103b

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AI03104b

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PART NUMBERING

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REVISION HISTORY

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